I have been running some tests with registers on an FPGA, specifically attempting to create a register ring and see what happens. Unfortunately, I have been getting an inverter loop where not desired (when the registers are released from reset, data lines start flipping). I did not get this behavior without the ring, so I think it’s more or less a delay problem in my design. Additionally, the simulator will not launch for me, which I am working on resolving. The up-side is that I have created several Vivado blocks, which are at least close to working (they appear to work when not in a ring). I believe that once I get the register ring working, I will be able to start moving on the larger designs (finite state machines, etc).
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