In this post, I described what a NCL register is. I wanted to get a more practical understanding of what the register does and how different pipeline stages interact. To facilitate this, I put the Full Adder between two registers, with their control signals linked:
In this setup, both registers start with NULL, requesting DATA.
- When DATA is fed to the first register, it immediately passes it on to the adder and requests NULL
- Once the Adder completes, the second register saves the DATA to the outputs and requests NULL.
The same sequence repeats with the NULL wavefront, then back to DATA, and so on…
We’ve already tested the Adder, but we want to make sure the system works, so we make a separate test for this unit (VHDL source, TCL test script). This test doesn’t actually verify the results of the computation as we already checked the adder. Essentially, if it runs, the pipelining worked. If it hangs, then something is wrong and wavefronts are not propagating through the circuit.
In theory, a loop with 3 registers can be made, but in this case, if the outputs feed back, the result will degrade to 1 eventually, or stay at 0. I may make a 2-bit counter or something in a while.
Commit: 40d96b8