An assortment of technical content
I haven’t posted in about a year now. I’m still not really back. I’ve been pouring my time into a Mars rover project that I will be a part of for another year. As the project goes on (we go to competition next summer) I may post things here, I will try to tag them with ‘MAVRIC’ to keep them straight.
My apologies for the very long silence and the lack of asynchronous logic content. I’ll be getting back to it eventually (or that’s the plan). Thanks for bearing with me.
I am transitioning back into school, and might not post for a bit.
Sorry.
To run a test, please make sure you have the correct version of the repository. Most posts that involve VHDL source will mention a commit, with a link (if you find a post that should have one and it doesn’t, please let me know).
Open ModelSim
If you are a student, you can get the PE student version from Mentor here, or your university might have it in a computer lab
Open the project file (NCL Gates/NCL Gates.mpf) with ModelSim.
Type source scripts/tests/[testname].tcl where [testname] is the name of a test file in the scripts/tests/ folder.
My tests should compile the dependencies automatically, but I might have missed something at some point, so let me know if it doesn’t work.
I want to explain the logo a bit:
It’s three relevant logic gates in one. The red portion is a Threshold Gate:
Threshold gates are used by NCL logic. The next gate is the blue one, you may recognize it as an AND gate. Some models of Asynchronous Logic use something called a C-Element, which is drawn like an AND-gate, but it has a ‘C’ in the middle (not shown in the logo). C-Elements are functionally identical to a TH22 gate.
The white portion in the middle was not actually something I planned, but I was quite pleased when I noticed the shape. It is the shape of an NCL Threshold gate without hysteresis. These gates aren’t (to my knowledge) used directly very often in designs, but they are the blocks that Threshold Gates with hysteresis are built on.
This is done by feeding the output back to the input m-1 times on an (n+m-1)-input non-hysteresis gate with the same m (see this post).
And of course I tried to make it all look sorta cool. Though I admit, it might be too complex for the 16×16 browser tab icon.
If you want, I can provide the GIMP project on GitHub. If you have suggestions for improvements, let me know.
Hey there, everyone. I am going to be posting my experiences here as I work through my asynchronous logic design projects. I’m a Computer Engineering undergrad student at Iowa State University. I will try to answer any questions as much as I can, but this is my first try at asynchronous designs, so I won’t have all the answers.
Anyways, thank you for taking a look and I hope you learn something. If you have a request for something, let me know and I can try it. Some things I thought of, but don’t know if people want: