So, I have been doing more reading, and I found a concept that I think I glossed over up to this point. Input Completeness is the condition that the output should not change until all inputs are available. This must hold for both NULL->DATA and DATA->NULL wavefronts. I don’t actually understand why this is necessary yet.

I had vaguely considered the concept as weather or not internal lines would ever toggle more than once during a single data cycle, but I thought that since all data was expressed by asserted lines, a system couldn’t toggle as long as there were no inverters. Even if there was feedback, none of the gates use compliments of inputs, so adding more inputs either sets the gate, or leaves it alone. There is no way to clear a set line, without clearing an input. I will look into the reasons this condition is necessary at some point.

Quick thing: I will be using the term CSOP a bunch. It means Canonical Sum-of-Product. This is the version of the equation that has all of the truth table rows brought out separately. Even if the function can be optimized to eliminate a variable from a term or two, that would violate the rules of CSOP.

The NULL->DATA Wavefront

If the circuit is initially NULL (inputs, outputs, internals) then the outputs cannot change until all inputs are DATA. The simplest way to do this is to use the CSOP implementation. With CSOP, every input is used in one of the AND-Plane gates (either as DATA0 or DATA1). As such, none of the AND-Plane gates can trigger until all of the inputs have values.

The AND-Plane is the column of THNN gates that all the inputs tie into (all possible combinations of input DATA values).

The DATA->NULL Wavefront

The DATA->NULL transition for any individual gate is held until all its inputs go to NULL. As such, once an output is set, it won’t clear until its inputs clear. Unfortunately that only applies to the inputs involved in setting the output; in CSOP, again, this is all of them. If the output is not constructed with CSOP, then in some cases, some inputs won’t affect the outputs (think the unselected inputs of a MUX).

Solutions

It is not necessary to implement the function with CSOP, you can take the logic function and add (A.0+A.1) to the product terms that are missing A, for example. The function can then be simplified/expanded from there. This is described some here on page 17 (section 3.1):

I haven’t found a openly available source for this, if you are a student, check your university’s library website. If you do find a source, comment it.

See this post for information about NCL signals.

Symbol

It may or may not surprise you to know that NCL has it’s own set of gates for building circuits. They are called threshold gates and are drawn as

with the ‘threshold number’ in the middle. The inputs come in on the left (round) part, and the output comes out the point on the right.

Operation

For all threshold gates:

• If all inputs are 0, the output is 0
• If the number of inputs that are set is >= the threshold number, the output is 1
• Otherwise, it holds its value.

threshold gates can have input weights, meaning that an input can count towards the threshold count more than once.

Notation

A threshold gate is denoted as THmn where m is the threshold value (the number of inputs needed to transition to a 1) and n is the total number of inputs. If weights are needed, then THmnW## is used, where the #’s are replaced with the weights (order is irrelevant). A TH23W2 gate sets when the first input is set (as it is counted twice), or when both of the other 2 are set. The boolean logic function is

TH23W2 Set: A+BC

Note that when just B or C are set, the gate keeps its value, so if it was a 1, then it will stay a 1, and if it was a 0 it will stay a 0. The logic function for clearing the gates is essentially the same for all:

THm1 Clear: A'
THm2 Clear: A'B'
THm3 Clear: A'B'C'
THm4 Clear: A'B'C'D

Summary

Threshold gates are used in NCL because they are less volatile than standard gates. Once they have an output, they hold on to int until their inputs are completely cleared (circuit reset). This means that a NCL component’s output will not flip more than once in an operation. This property of threshold gates means that if the outputs are set, the component has completed, and if they are reset, it has cleared. You always know when it is ready to move on.

If you don’t yet know what asynchronous logic is, I recommend reading this post (or using Google).

For the time being, I will be focusing my efforts on Null Convention Logic (NCL). NCL is technically a separate logic system from boolean logic. For now, I’ll stick to considering it in the context of a boolean system. What that means is that all signals in the design will still be boolean, they will just represent something a little different.

In NCL, each signal (boolean value) still has 2 meanings, but they are changed. A value of 0 means NO_DATA/NULL and a value of 1 means DATA. Different signals have different Data assigned. To represent a standard boolean variable, 2 lines are needed, the encoding:

• FALSE (0): DATA0=1, DATA1=0
• TRUE (1): DATA0=0, DATA1=1
• Null/Unknown: DATA0=0, DATA1=0

The new state, NULL is used when the circuit hasn’t determined a value for the line yet. Detecting completion of the circuit is then as simple as seeing if one line in each group is set. When all the outputs are assigned a value, the values are saved, and the circuit resets to NULL outputs.

Note, it is entirely possible to have more than two lines in a group. Imagine If I made a circuit that took in an 8-bit color value and outputted if it was mostly one of {Red, Green, Blue}. Instead of having 2 boolean variables for 3 states (wasting a combination), I can have 1 three-state variable: {DATA_RED, DATA_BLUE, DATA_GREEN}. When the circuit is reset, the output is unknown, so all three go to NULL, when the inputs are received and the result found, the circuit sets one of the lines. This is not that different from ‘one-hot’ encoding in synchronous logic, except that it does have a defined all-off state that carries meaning (not data, but it does indicate circuit state). In synchronous logic, such a state would be an error.

The most common encodings I’ve come across so far are 2-rail {DATA0 and DATA1} and 4-rail {DATA0, DATA1, DATA2, DATA3}, representing 1 and 2 boolean variables respectively.

Anyways, that’s the basics of NCL signaling. The thing to remember is that the signals have to go to NULL between calculations, otherwise, there’s no way to know when they are ready.